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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 8.0V ≤ V PWR = V BAT ≤ 40V, -40 ° C ≤ T A ≤ 125 ° C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE TIMING
Maximum Frequency of SPI Operation
f OP
–
5.0
MHz
Internal Time Base
f TB
13
17
25
MHz
Internal Time Base drift from value at 25 ° C
(44)
TC TB
-5
–
5
%
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
(44)
(44)
t LEAD
t LAG
100
100
–
–
–
–
ns
ns
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
(44)
(44)
t SISU
t SIHOLD
25
25
–
–
–
–
ns
ns
,
SI, CS, SCLK Signal Rise Time
(44) (45)
t RSI
–
5.0
–
ns
,
SI, CS, SCLK Signal Fall Time
(44) (45)
t FSI
–
5.0
–
ns
,
Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
(44) , (46)
(44) (47)
t SOEN
t SODIS
–
–
55
100
100
125
ns
ns
,
Time from Rising Edge of SCLK to SO Data Valid
(44) (48)
t VALID
–
55
100
ns
Time from Rising Edge of CS to Falling Edge of the next CS
(44)
t DT
200
–
–
ns
Notes
44.
45.
46.
47.
48.
This parameter is guaranteed by design, not production tested.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
33927
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
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